Conventional devices will be scaled down to its physical limitations in 10-15 years. However, during this period, new device structures, for example carbon nanotubes (CNT), spintronic devices and molecular switches, etc, may not be developed to a level of practical application. Therefore, in such a case where copper and low k dielectric materials are used for integration, new methods for device-level and system-level assembly are sought for industrial applications, so as to meet recent demands. Three-dimension (3D) integrated circuits (ICs) are the most advanced technique, which may shorten the length of interconnects, thereby improving speed of circuits, reducing power consumption, and increasing system storage bandwidth.
The current 3D IC integration is described as a system-level architecture formed by combination of a plurality of wafers, wherein each wafer is a stack of a plurality of planar device layers interconnected in a Z direction by though-silica-vias (TSVs). With the application of 3D ICs, the size of TSVs will be scaled continuously, the thickness of silicon layer will also be thinned, and the 3D integration circuits will be more widely used.
However, in some processes of forming a 3D integrated circuit structure, for example in a process of forming a TSV, metal materials such as copper, aluminum, and tungsten, etc., will be filled into the TSV. Besides, in a process of grinding the bottom of a wafer to expose the metal material in the TSV so as to be bonded with other wafers, the metal material or other dopants, for example metal ions such as iron and sodium, etc, exposed at the bottom of the TSV, will be diffused into the metal oxide semiconductor field effect transistor (MOSFET) in the wafer because of the grinding process. Further, in the following process of inter-bonding of wafers, the above variety of metal ions are rapidly diffused into the MOSFET due to the bonding high temperature. Thus, failures will occur to the formed MOSFET.